A 5-GHz CMOS double-quadrature receiver for IEEE 802.11a applications

被引：6
|
作者：
Wu, CY [1 ]
Chou, CY [1 ]
机构：
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
来源：
2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2003年
关键词：
D O I：
10.1109/VLSIC.2003.1221186
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0.18um CMOS technology, the receiver chip can achieve 50.6dB image-rejection with the power dissipation of 22.4mW at 1.8-V voltage supply.
引用
收藏
页码：149 / 152
页数：4
相关论文
共 50 条
  • [41] Compact quadrature receiver for 24 GHz radar applications in 0.13 μm CMOS
    Issakov, V.
    Mertens, K. L. R.
    Tiebout, M.
    Thiede, A.
    Simbuerger, W.
    [J]. ELECTRONICS LETTERS, 2010, 46 (01) : 79 - U111
  • [42] Receiver window design for narrowband interference suppression in IEEE 802.11a system
    Zhang, D
    Fan, PY
    Cao, ZG
    [J]. 2004 JOINT CONFERENCE OF THE 10TH ASIA-PACIFIC CONFERENCE ON COMMUNICATIONS AND THE 5TH INTERNATIONAL SYMPOSIUM ON MULTI-DIMENSIONAL MOBILE COMMUNICATIONS, VOLS 1 AND 2, PROCEEDINGS, 2004, : 839 - 842
  • [43] A 5-GHz BiCMOS RFIC front-end for IEEE 802.11 a/HiperLAN wireless LAN
    Margarit, MA
    Shih, D
    Sullivan, PJ
    Ortega, F
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (07) : 1284 - 1287
  • [44] A 3.2 to 4GHz, 0.25μm CMOS frequency synthesizer for IEEE 802.11a/b/g WLAN
    Terrovitis, M
    Mack, M
    Singh, K
    Zargari, M
    [J]. 2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 : 98 - 99
  • [45] Receiver-based packet combining in IEEE 802.11a wireless LAN
    Gidlund, M
    [J]. BOSTON 2003 RADIO & WIRELESS RAWCON CONFERENCE, PROCEEDINGS, 2003, : 47 - 50
  • [46] A 5.8-GHz high efficient, low power, low phase noise CMOS VCO for IEEE 802.11a
    Wu, SM
    Liu, RY
    Chen, WL
    [J]. 3RD IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2003, : 94 - 97
  • [47] 可用于无线局域网802.11a标准的5-GHz CMOS功率放大器设计
    宗国翼
    朱恩
    李智群
    [J]. 电子器件, 2005, (01) : 161 - 163
  • [48] A 4GHz fractional-N synthesizer for IEEE 802.11a
    Chien, HM
    Lin, TH
    Ibrahim, B
    Zhang, LJ
    Rofougaran, M
    Rofougaran, A
    Kaiser, WJ
    [J]. 2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, : 46 - 49
  • [49] Microstrip Patch Antenna for IEEE 802.11a WLAN (5.25 GHz) Application
    Tyagi, Charu
    Joshi, Ira
    Porwal, Shalini
    [J]. PROCEEDINGS OF INTERNATIONAL CONFERENCE ON ICT FOR SUSTAINABLE DEVELOPMENT, ICT4SD 2015, VOL 1, 2016, 408 : 361 - 367
  • [50] A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling
    Gierkink, SLJ
    Levantino, S
    Frye, RC
    Samori, C
    Boccuzzi, V
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (07) : 1148 - 1154
12345