A 5-GHz CMOS double-quadrature receiver for IEEE 802.11a applications

被引：6
|
作者：
Wu, CY [1 ]
Chou, CY [1 ]
机构：
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
来源：
2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2003年
关键词：
D O I：
10.1109/VLSIC.2003.1221186
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0.18um CMOS technology, the receiver chip can achieve 50.6dB image-rejection with the power dissipation of 22.4mW at 1.8-V voltage supply.
引用
收藏
页码：149 / 152
页数：4
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