Design of an efficient VLSI architecture for 2-D discrete wavelet transforms

被引：12

作者：

Yu, C ^{[1
]}

Chen, SJ ^{[1
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10764, Taiwan

来源：

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS | 1999年 / 45卷 / 01期

关键词：

D O I：

10.1109/30.754428

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present a VLSI architecture for the separable two-dimensional Discrete Wavelet Transform (DWT) decomposition. Using a computation-schedule table, we showed how the proposed separable architecture uses only a minimal number of filters to generate all levels of DWT computations in real time. For the computation of an N x N 2-D DWT with a filter length L, this architecture spends around N-2 clock cycles, and requires 2NL-2N storage unit, 3L multipliers, as well as 3(L-1) adders.

引用

页码：135 / 140

页数：6

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