High-Speed Low-Power Viterbi Decoder Design for TCM Decoders

被引：17

作者：

He, Jinjin ^{[1
]}

Liu, Huaping ^{[1
]}

Wang, Zhongfeng ^{[2
]}

Huang, Xinming ^{[3
]}

Zhang, Kai ^{[3
]}

机构：

[1] Oregon State Univ, Sch Elect Engn & Comp Sci, Corvallis, OR 97331 USA

[2] Broadcom Corp, Irvine, CA 92617 USA

[3] Worcester Polytech Inst, Dept Elect & Comp Engn, Worcester, MA 01609 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2012年 / 20卷 / 04期

基金：

美国国家科学基金会;

关键词：

Trellis coded modulation (TCM); viterbi decoder; VLSI;

D O I：

10.1109/TVLSI.2011.2111392

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. We propose a pre-computation architecture incorporated with T-algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible.

引用

下载

页码：755 / 759

页数：5

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