High-Speed Low-Power Viterbi Decoder Design for TCM Decoders

被引：17

作者：

He, Jinjin ^{[1
]}

Liu, Huaping ^{[1
]}

Wang, Zhongfeng ^{[2
]}

Huang, Xinming ^{[3
]}

Zhang, Kai ^{[3
]}

机构：

[1] Oregon State Univ, Sch Elect Engn & Comp Sci, Corvallis, OR 97331 USA

[2] Broadcom Corp, Irvine, CA 92617 USA

[3] Worcester Polytech Inst, Dept Elect & Comp Engn, Worcester, MA 01609 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2012年 / 20卷 / 04期

基金：

美国国家科学基金会;

关键词：

Trellis coded modulation (TCM); viterbi decoder; VLSI;

D O I：

10.1109/TVLSI.2011.2111392

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. We propose a pre-computation architecture incorporated with T-algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible.

引用

页码：755 / 759

页数：5

共 50 条

[1] Design of High Speed Low Power Viterbi Decoder for TCM System
Nargis, J.
Vaithiyanathan, D.
Seshasayanan, R.
[J]. 2013 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2013, : 185 - 190
[2] VLSI implementation of a high-speed and low-power punctured Viterbi decoder
Li, Q
You, YX
Wang, JX
Ye, YZ
[J]. 2002 IEEE REGION 10 CONFERENCE ON COMPUTERS, COMMUNICATIONS, CONTROL AND POWER ENGINEERING, VOLS I-III, PROCEEDINGS, 2002, : 1205 - 1208
[3] An efficient metric normalization architecture for high-speed low-power Viterbi Decoder
Lai, Kelvin Yi-Tse
[J]. TENCON 2007 - 2007 IEEE REGION 10 CONFERENCE, VOLS 1-3, 2007, : 1500 - 1503
[4] The design of high-speed and low power consumption bidirection Viterbi decoder
Li, Song
Yi, Qing-Ming
[J]. PROCEEDINGS OF 2006 INTERNATIONAL CONFERENCE ON MACHINE LEARNING AND CYBERNETICS, VOLS 1-7, 2006, : 3886 - +
[5] A new low-power and high speed viterbi decoder architecture
Choi, Chang-Jin
Yoon, Sang-Hun
Chong, Jong-Wha
Lin, Shouyin
[J]. UBIQUITOUS CONVERGENCE TECHNOLOGY, 2007, 4412 : 283 - +
[6] Low-power register-exchange Viterbi Decoder for high-speed wireless communications
El-Dib, DAF
Elmasry, MI
[J]. 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS, 2002, : 737 - 740
[7] A high-speed, low-power interleaved trace-back memory for Viterbi Decoder
Israsena, Pasin
Kale, Izzet
[J]. 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 2801 - 2804
[8] High-speed and low-power design of parallel turbo decoder
He, ZY
Roy, S
Fortier, P
[J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 6018 - 6021
[9] Design and Implementation of Low Power High Speed Viterbi Decoder
Cholan, K.
[J]. INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY AND SYSTEM DESIGN 2011, 2012, 30 : 61 - 68
[10] Design of low-power high-speed maximum a priori decoder architectures
Worm, A
Lamm, H
Wehn, N
[J]. DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, 2001, : 258 - 265

← 1 2 3 4 5 →