Impact of process scaling on 1/f noise in advanced CMOS technologies

被引：38

作者：

Knitel, MJ ^{[1
]}

Woerlee, PH ^{[1
]}

Scholten, AJ ^{[1
]}

Zegers-Van Duijnhoven, ATA ^{[1
]}

机构：

[1] Philips Res Labs, NL-5656 AA Eindhoven, Netherlands

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904356

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The influence of the gate-oxide thickness, the substrate dope, and the gate bias on the input-referred spectral l/f noise density Sv(gate) has been experimentally investigated. It is shown that the dependence on the oxide thickness and the gate bias can be described by the model of Hung, and that Sv(gate) can be predicted for future technologies. Discrepancies with the ITRS roadmap are discussed.

引用

页码：463 / 466

页数：4

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