BIST-based test and diagnosis of FPGA logic blocks

被引:70
|
作者
Abramovici, M [1 ]
Stroud, CE
机构
[1] Lucent Technol, Murray Hill, NJ 07974 USA
[2] Univ Kentucky, Dept Elect Engn, Lexington, KY 40506 USA
基金
美国国家科学基金会;
关键词
built-in self-test; fault-tolerance; FPGA diagnosis; FPGA testing; reconfigurable systems;
D O I
10.1109/92.920830
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution, Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation, We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs, Our BIST architecture is easily scalable.
引用
收藏
页码:159 / 172
页数:14
相关论文
共 50 条
  • [41] A New BIST-based Test Approach with the Fault Location Capability for Communication Channels in Network-on-Chip
    Aghaei, Babak
    Khademzadeh, Ahmad
    Reshadi, Midia
    Badie, Kambiz
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2017, 33 (04): : 501 - 513
  • [42] BIST-BASED DIGITAL DESIGN FOR IEEE 1394B PHY
    Wen, Zhang
    Liu, HaiQi
    Li, Qiang
    2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2014,
  • [43] Behavioral test generation for the selection of BIST logic
    Biasoli, G
    Ferrandi, F
    Fin, A
    Fummi, F
    Sciuto, D
    JOURNAL OF SYSTEMS ARCHITECTURE, 2002, 47 (10) : 821 - 829
  • [44] Programmable logic BIST for at-speed test
    Huang, Yu
    Lin, Xijiang
    PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM, 2007, : 295 - +
  • [45] BIST based fault diagnosis using ambiguous test set
    Takahashi, H
    Tsugaoka, Y
    Ayano, H
    Takamatsu, Y
    18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2003, : 89 - 96
  • [46] Reducing Test Power and Improving Test Effectiveness for Logic BIST
    Wang Weizheng
    Cai Shuo
    Xiang Lingyun
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2014, 14 (05) : 640 - 648
  • [47] Performance Evaluation Based on Placement Planning of Logic Blocks in FPGA Design
    Joseph, Jasmine
    Chalil, Anu
    2018 INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, SIGNAL PROCESSING AND NETWORKING (WISPNET), 2018,
  • [48] Analysis of FPGA Architecture with Hybrid Logic Blocks Based on ULG and LUT
    Sudhanya, P.
    Rani, S. P. Joy Vasantha
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2024,
  • [49] Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
    Stroud, C
    Konala, S
    Chen, P
    Abramovici, M
    14TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1996, : 387 - 392
  • [50] A Built-In Self-Test (BIST) system with non-intrusive TPG and ORA for FPGA test and diagnosis
    Ruan, Aiwu
    Kang, Shi
    Wang, Yu
    Han, Xiao
    Zhu, Zujian
    Liao, Yongbo
    Li, Peng
    MICROELECTRONICS RELIABILITY, 2013, 53 (03) : 488 - 498