Programmable logic BIST for at-speed test

被引：7
|
作者：
Huang, Yu [1 ]
Lin, Xijiang [2 ]
机构：
[1] Mentor Graph Corp, 300 Nickerson Rd, Marlborough, MA 01752 USA
[2] Mentor Graph Corp, Wilsonville 97068, OR USA
来源：
PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM | 2007年
关键词：
D O I：
10.1109/ATS.2007.83
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we propose a novel programmable logic BIST controller that can facilitate at-speed test for the design with multiple clock domains and multiple clock frequencies. Moreover, a static analysis method is also proposed to optimize the BIST test pattern allocation for testing the timing faults in different intra/inter clock domains when the maximum number of applied BIST test patterns is specified Experimental results show the effectiveness of the proposed method on achieving higher test coverage than the method with test patterns evenly distributed among different test sessions.
引用
收藏
页码：295 / +
页数：2
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