Programmable logic BIST for at-speed test

被引：7

作者：

Huang, Yu ^{[1
]}

Lin, Xijiang ^{[2
]}

机构：

[1] Mentor Graph Corp, 300 Nickerson Rd, Marlborough, MA 01752 USA

[2] Mentor Graph Corp, Wilsonville 97068, OR USA

来源：

PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM | 2007年

关键词：

D O I：

10.1109/ATS.2007.83

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we propose a novel programmable logic BIST controller that can facilitate at-speed test for the design with multiple clock domains and multiple clock frequencies. Moreover, a static analysis method is also proposed to optimize the BIST test pattern allocation for testing the timing faults in different intra/inter clock domains when the maximum number of applied BIST test patterns is specified Experimental results show the effectiveness of the proposed method on achieving higher test coverage than the method with test patterns evenly distributed among different test sessions.

引用

页码：295 / +

页数：2

共 50 条

[21] Design of Efficient Programmable Test-per-Scan Logic BIST Modules
Devika, K. N.
Bhakthavatchalu, Ramesh
2017 INTERNATIONAL CONFERENCE ON MICROELECTRONIC DEVICES, CIRCUITS AND SYSTEMS (ICMDCS), 2017,
[22] A Comprehensive TCAM Test Scheme: An Optimized Test Algorithm Considering Physical Layout and Combining Scan Test with At-Speed BIST Design
Wu, Hsiang-Huang
Lee, Jih-Nung
Chiang, Ming-Cheng
Liu, Po-Wei
Wu, Chi-Feng
ITC: 2009 INTERNATIONAL TEST CONFERENCE, 2009, : 186 - +
[23] At-Speed BIST for Interposer Wires Supporting On-the-Spot Diagnosis
Huang, Shi-Yu
Lee, Jeo-Yen
Tsai, Kun-Han
Cheng, Wu-Tung
PROCEEDINGS OF THE 2013 IEEE 19TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 2013, : 67 - 72
[24] At-Speed Path Delay Test
Chakraborty, Swati
Walker, D. M. H.
2015 IEEE 24TH NORTH ATLANTIC TEST WORKSHOP (NATW), 2015, : 39 - 42
[25] Achieving at-speed structural test
Pateras, S
IEEE DESIGN & TEST OF COMPUTERS, 2003, 20 (05): : 26 - 33
[26] Embedded at-speed test probe
Aigner, M
ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY, 1997, : 932 - 937
[27] A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST
Sakakibara, H
Nakayama, M
Kusunoki, M
Kurita, K
Otori, H
Hasegawa, M
Iwahashi, S
Higeta, K
Hanashima, T
Hayashi, H
Kuchimachi, K
Uehara, K
Nishiyama, T
Kume, M
Miyamoto, K
Kamada, E
2003 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE: DIGEST OF TECHNICAL PAPERS, 2003, 46 : 458 - +
[28] Diagnosing at-speed scan BIST circuits using a low speed and low memory tester
Nakamura, Yoshiyuki
Clouqueur, Thomas
Saluja, Kewal K.
Fujiwara, Hideo
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2007, 15 (07) : 790 - 800
[29] Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation
Li, Fuqiang
Wen, Xiaoqing
Miyase, Kohei
Holst, Stefan
Kajihara, Seiji
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2016, E99A (12) : 2310 - 2319
[30] Error identification in at-speed scan BIST environment in the presence of circuit and tester speed mismatch
Nakamura, Y
Clouqueur, T
Saluja, KK
Fujiwara, H
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2006, E89D (03): : 1165 - 1172

← 1 2 3 4 5 →