Design and Implementation of FFT Pruning Algorithm on FPGA

被引：0
|
作者：
Kumar, Ch. Vinodh [1 ]
Sastry, K. R. K. [1 ]
机构：
[1] GVP Coll Engn A, Dept ECE, Visakhapatnam, Andhra Prades, India
来源：
PROCEEDINGS OF THE 7TH INTERNATIONAL CONFERENCE ON CLOUD COMPUTING, DATA SCIENCE AND ENGINEERING (CONFLUENCE 2017) | 2017年
关键词：
FFT; Radix-2; Verilog; FPGA; OFDM;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Digital Signal Processing (DSP) has evolved as an integrated component in electronics advancement. Among all the DSP operations, Fast Fourier Transform (FFT) plays a prominent role in signal processing. FFT computational time reduces when the number of zero valued inputs (Z) outnumbers the non-zero valued inputs (NZ) due to unnecessary computations for Z. The above issue can be resolved by minimizing computations on Z by the method Pruning (Partial, Complete) in FFT. The pruning method is implemented in the hardware and computational time improvement is observed. The FFT Pruning is developed in Verilog and validated on Spartan 3E FPGA (xc3s500e-fg320-5).
引用
收藏
页码：739 / 743
页数：5
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