Pulsed PMOS Sense Amplifier for High Speed Single-Ended SRAM

In this paper, a pulsed pMOS sense amplifier for single-ended static random access memory (SRAM) at low supply voltage is proposed. Domino logic for single-ended SRAM such as 8T SRAA4 has a large read delay because a large read bitline swing is required. To improve read delay, previously proposed pseudo nMOS based sense amplifier was proposed. However, it has a large static current, which causes a large energy consumption. With 22nm FinFET technology, the proposed pulsed pMOS sense amplifier improves read delay by about 80% compared with conventional domino logic and reduces energy consumption by 40% compared with previously proposed pseudo nMOS based sense amplifier.