On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals

被引：7
|
作者：
Zhang, Ling [1 ]
Zhang, Yulei [2 ]
Chen, Hongyu
Yao, Bo [3 ]
Hamilton, Kevin [2 ]
Cheng, Chung-Kuan [1 ]
机构：
[1] Univ Calif San Diego, Dept Comp Sci & Engn, La Jolla, CA 92037 USA
[2] Univ Calif San Diego, Dept Elect & Comp Engn, La Jolla, CA 92037 USA
[3] Mentor Graph Corp, Wilsonville, OR 97070 USA
来源：
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2011年 / 19卷 / 03期
基金：
美国国家科学基金会;
关键词：
Analysis; energy-delay optimization; high speed; interconnect; low power;
D O I：
10.1109/TVLSI.2009.2035322
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
As semiconductor process technology scales down, interconnect planning presents ever-greater challenges to designers. In this paper, we analyze, evaluate, and compare various metrics with optimized wire configurations in the contexts of different design criteria: delay minimization, delay-power minimization, and delay(2)-power minimization. We show how various design criteria influence the configuration, performance, and power consumption of repeated wires.
引用
收藏
页码：520 / 524
页数：6
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