Performance Optimization of High Speed DACs Using DSP

DSP techniques that enhance the effective resolution of digital-to-analog converters (DACs) are presented. First, DACs that are limited by physical number of bits (PNOB) are addressed. An improved digital-resolution-enhancer (DRE) algorithm, which incorporates an optimized non-uniform quantization scheme is analytically analyzed and experimentally demonstrated. Improvement of up to 8 dB is shown, that enables 16QAM and 64QAM transmission using only 2 and 3 bits DACs, respectively. Furthermore, the DRE concept is elaborated to include additional practical DAC impairments such as timing jitter. Based on a generalized DAC model, we suggest an improved algorithm that increases the tolerance to jitter noise, termed as jitter-aware DRE (JA-DRE). The method is validated in numerical simulations, indicating substantial OSNR gain of similar to 5 dB over non DSP enhanced DACs, and up to 2 dB over the previously proposed DRE algorithm.