A NOVEL HSPICE MACRO MODEL FOR THE ESD BEHAVIOR OF GATE GROUNDED NMOS AND GATE COUPLED NMOS

被引：0

作者：

Yang, Shao Ming ^{[1
]}

Hema, E. P.

Sheu, Gene ^{[1
]}

Mrinal, Aryadeep

Amanullah, Md

Chen, P. A. ^{[2
]}

机构：

[1] Asia Univ, Dept Comp Sci & Informat Engn, Taichung, Taiwan

[2] Nuvoton Technol Corp, Hsinchu, Taiwan

来源：

2015 China Semiconductor Technology International Conference | 2015年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper an Hspice macro model is presented to model the snapback characteristics of GGNMOS (gate-grounded NMOS) and GCNMOS (gate-coupled NMOS) under ESD stress. The 5V NMOS be simulated in this paper is based on the 0.35um BCD technology as an ESD protection device. The new macro model has successfully predicted the trigger voltage and holding voltage of the GGNMOS and GCNMOS according to the silicon data. The effects of device parameters Tref and Rs exhibit a good trend curve in agreement with BJT model, which helps for the prediction of the trigger voltage and holding voltage for ESD circuit application.

引用

页数：3

共 50 条

[41] Gate-Lifted nMOS ESD Protection Device Triggered by a p-n-p in Series With a Diode
Lai, Da-Wei
Sque, Stephen
Peters, Wim
Smedes, Theo
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (04) : 1642 - 1647
[42] Investigation of gate to contact spacing effect on ESD robustness of salicided deep submicron single finger NMOS transistors
Oh, KH
Duvvury, C
Banerjee, K
Dutton, RW
40TH ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2002, : 148 - 155
[43] Characteristics of Ni/Gd FUSI for NMOS gate electrode applications
Lee, Bongmook
Biswas, Nivedita
Novak, Steven R.
Misra, Veena
IEEE ELECTRON DEVICE LETTERS, 2007, 28 (07) : 555 - 557
[44] Closed-form partitioned gate tunneling current model for NMOS devices with an ultra-thin gate oxide
Lin, C. H.
Kuo, J. B.
SOLID-STATE ELECTRONICS, 2009, 53 (11) : 1191 - 1197
[45] An Nmos Cross-Coupled Quadrature Vco using Coupling Common-Gate Pmosfets
Jang, Sheng-Lyang
Lin, Hsi-Han
Hsue, Ching-Wen
MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2013, 55 (08) : 1705 - 1708
[46] MODELING OF ULTRATHIN DOUBLE-GATE NMOS/SOI TRANSISTORS
FRANCIS, P
TERAO, A
FLANDRE, D
VANDEWIELE, F
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1994, 41 (05) : 715 - 720
[47] Characterization of Gate Oxide Pinhole Defect in NMOS FinFET Devices
Chen, Liangshan
Bousquet, Arnaud
Schaeffer, Tanya
Sheridan, Lucile C. Teague
Hodgkins, Lowell
Fu, Bianzhu
Oh, Chongkhiam
ISTFA 2017: CONFERENCE PROCEEDINGS FROM THE 43RD INTERNATIONAL SYMPOSIUM FOR TESTING AND FAILURE ANALYSIS, 2017, : 451 - 455
[48] NMOS gate electrode selection process for advanced silicon devices
Misra, V
Heuss, G
Suh, YS
Zhong, HC
Lee, JH
RAPID THERMAL AND OTHER SHORT-TIME PROCESSING TECHNOLOGIES III, PROCEEDINGS, 2002, 2002 (11): : 225 - 234
[49] On the Breakdown Physics of Trench-Gate Drain Extended NMOS
Tailor, Ketankumar H.
Shrivastava, Mayank
Gossner, Harald
Baghini, Maryam Shojaei
Rao, V. Ramgopal
PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2015, : 804 - 807
[50] Second breakdown of 18V grounded gate NMOS induced by the Kirk effect under electrostatic discharge
Jeon, BC
Lee, SC
Han, MK
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2003, 42 (9A): : 5516 - 5520

← 1 2 3 4 5 →