Fast Statistical Timing Analysis for Circuits with Post-Silicon Tunable Clock Buffers

被引：0

作者：

Li, Bing ^{[1
]}

Chen, Ning ^{[1
]}

Schlichtmann, Ulf ^{[1
]}

机构：

[1] Tech Univ Munich, Inst Elect Design Automat, D-8000 Munich, Germany

来源：

2011 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) | 2011年

关键词：

NON-GAUSSIAN PARAMETERS; CRITICALITY COMPUTATION;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Post-Silicon Tunable (PST) clock buffers are widely used in high performance designs to counter process variations. By allowing delay compensation between consecutive register stages, PST buffers can effectively improve the yield of digital circuits. To date, the evaluation of manufacturing yield in the presence of PST buffers is only possible using Monte Carlo simulation. In this paper, we propose an alternative method based on graph transformations, which is much faster, more than 1000 times, and computes a parametric minimum clock period. It also identifies the gates which are most critical to the circuit performance, therefore enabling a fast analysis-optimization flow.

引用

页码：111 / 117

页数：7

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