Nanoscale epitaxial cobalt salicide bitlines for charge trapping memory cells

被引:1
|
作者
Kleint, C. A. [1 ]
Mueller, T. [1 ]
Teichert, S. [1 ]
Fitz, C. [1 ]
Nagel, N. [1 ]
Kuesters, K. H. [1 ]
机构
[1] Qimonda Dresden GmbH & Co, OHG, D-01099 Dresden, Germany
关键词
D O I
10.1063/1.2906366
中图分类号
O59 [应用物理学];
学科分类号
摘要
An epitaxial CoSi2 process is presented, which allows the self-aligned formation of bitlines with only a few tens of nanometer width for Twin Flash memory cells in the 63 nm generation. The bitlines show a good thermal stability and low resistance for widths down to 35 nm, where polycrystalline CoSi2 is known to exhibit a strong narrow linewidth effect. Transmission electron microscopy studies revealed a cube-on-cube epitaxy with only a few twins depending on the annealing conditions. The low bitline resistance results in a linear drain voltage dependence of the programing characteristics and a suppression of secondary electron injection during programing. (C) 2008 American Institute of Physics.
引用
收藏
页数:3
相关论文
共 50 条
  • [1] Localized charge trapping memory cells in a 63 nm generation with nanoscale epitaxial cobalt salicide buried bitlines
    Mueller, Torsten
    Kleint, C.
    Fitz, C.
    Isler, M.
    Riedel, S.
    Sachse, J. -U.
    Olligs, D.
    Boubekeur, H.
    Heinrichsdorf, F.
    Polei, V.
    Pritchard, D.
    Verhoeven, M.
    Lattard, L.
    Markert, M.
    Schupke, C.
    Tippelt, B.
    Teichert, S.
    Reisdorf, R.
    Ludwig, C.
    Kamienski, E. G. Stein V.
    Mikolajick, T.
    Nagel, N.
    MATERIALS AND PROCESSES FOR NONVOLATILE MEMORIES II, 2007, 997 : 65 - +
  • [2] Anomalous erase behavior in charge trapping memory cells
    Beug, M. F.
    Melde, T.
    Isler, M.
    Bach, L.
    Ackermann, M.
    Riedel, S.
    Knobloch, K.
    Ludwig, C.
    2008 JOINT NON-VOLATILE SEMICONDUCTOR MEMORY WORKSHOP AND INTERNATIONAL CONFERENCE ON MEMORY TECHNOLOGY AND DESIGN, PROCEEDINGS, 2008, : 121 - 123
  • [3] Charge trapping and scattering in epitaxial graphene
    Farmer, Damon B.
    Perebeinos, Vasili
    Lin, Yu-Ming
    Dimitrakopoulos, Christos
    Avouris, Phaedon
    PHYSICAL REVIEW B, 2011, 84 (20)
  • [4] Charge Trapping NanoElectronic Memory
    Lorenzi, P.
    Rao, R.
    Palma, F.
    Irrera, F.
    Ghidini, G.
    2009 9TH IEEE CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO), 2009, : 214 - 217
  • [5] Charge Trapping in Monolayer and Multilayer Epitaxial Graphene
    Liu, Chieh-, I
    Wang, Pengjie
    Mi, Jian
    Lee, Hsin-Yen
    Zhang, Chi
    Lin, Xi
    Chuang, Chiashain
    Aoki, Nobuyuki
    Elmquist, Randolph E.
    Liang, Chi-Te
    JOURNAL OF NANOMATERIALS, 2016, 2016
  • [6] Threshold voltage instability of nanoscale charge trapping non-volatile memory at steady phase
    Lee, Meng Chuan
    Wong, Hin Yong
    Lee, Lini
    MICROELECTRONICS RELIABILITY, 2014, 54 (11) : 2392 - 2395
  • [7] A nanoscale memory and transistor using backside trapping
    Silva, H
    Tiwari, S
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2004, 3 (02) : 264 - 269
  • [8] Nanoscale magnetic domain structures in epitaxial cobalt films
    Hehn, M
    Padovani, S
    Ounadjela, K
    Bucher, JP
    PHYSICAL REVIEW B, 1996, 54 (05): : 3428 - 3433
  • [9] Investigation on X-ray irradiation on nanoscale nitride based charge trapping flash memory devices
    Lee, Meng Chuan
    Wong, Hin Yong
    MICROELECTRONICS RELIABILITY, 2017, 79 : 59 - 68
  • [10] Charge Trapping Non Volatile Memory
    Lorenzi, P.
    Rao, R.
    Ghidini, G.
    Palma, F.
    Irrera, F.
    ULSI PROCESS INTEGRATION 6, 2009, 25 (07): : 269 - 276