Empirical modeling of oxide CMP at chip scale

被引:3
|
作者
Wolf, H [1 ]
Streiter, R
Rzehak, R
Meyer, F
Springer, G
机构
[1] Fraunhofer Inst Reliabil & Microintegrat, Dept Micro Devices & Equipment, D-09126 Chemnitz, Germany
[2] Infineon Technol, D-01099 Dresden, Germany
关键词
oxide CMP; modeling; chip scale;
D O I
10.1016/j.mee.2005.07.085
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We present an extension of the density-step height model for pattern effects in oxide chemical mechanical planarization. The model is compared to polishing data for processes using different pressure and speed. Agreement with the data is improved especially in the initial regime of polishing before the pad contacts down the areas. Implications for process optimization are discussed. (c) 2005 Elsevier B.V. All rights reserved.
引用
收藏
页码:686 / 694
页数:9
相关论文
共 50 条
  • [31] Empirical Modeling of Iron Oxide Dissolution in Sulphuric and Hydrochloric Acid
    Hemmelmann, Jan C.
    Xu, Hao
    Krumm, Wolfgang
    METALLURGICAL AND MATERIALS TRANSACTIONS B-PROCESS METALLURGY AND MATERIALS PROCESSING SCIENCE, 2013, 44 (05): : 1232 - 1235
  • [32] Compact modeling approaches to multiple die stacked chip scale packages
    Garcia, EA
    Chiu, CP
    NINETEENTH ANNUAL IEEE SEMICONDUCTOR THERMAL MEASUREMENT AND MANAGEMENT SYMPOSIUM, 2003, : 160 - 167
  • [33] CMP interfacial fluid pressure and modeling
    Shan, L
    Danyluk, S
    PROCEEDINGS OF THE FOURTEENTH ANNUAL MEETING OF THE AMERICAN SOCIETY FOR PRECISION ENGINEERING, 1999, : 139 - 145
  • [34] Mathematical modeling of CMP conditioning process
    Chang, Onemoon
    Kim, Hyoungjae
    Park, Kihyun
    Park, Boumyoung
    Seo, Heondeok
    Jeong, Haedo
    MICROELECTRONIC ENGINEERING, 2007, 84 (04) : 577 - 583
  • [35] FEOL CMP Modeling: Progress and Challenges
    Ghulghazaryan, Ruben
    Wilson, Jeff
    Abouzeid, Ahmed
    2015 INTERNATIONAL CONFERENCE ON PLANARIZATION/CMP TECHNOLOGY (ICPT), 2015,
  • [36] Modeling for Critical Design and Performance of Wafer Level Chip Scale Package
    Liu, Yong
    Qian, Qiuxiao
    Ring, Matt
    Kim, Jihwan
    Kinzer, Dan
    2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 1174 - 1182
  • [37] Accurate chip scale topography modeling in O(n) run time
    Lucas, KD
    Li, XL
    Noell, M
    Yuan, CM
    Strojwas, AJ
    SISPAD '96 - 1996 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 1996, : 159 - 160
  • [38] Atomic-scale magnetic modeling of oxide nanoparticles
    Kodama, RH
    Berkowitz, AE
    PHYSICAL REVIEW B, 1999, 59 (09): : 6321 - 6336
  • [39] CMP-APC based on nonlinear process model (1st report) polishing process modeling of oxide-film CMP with ceria slurry
    Morisawa T.
    Kobayashi H.
    Sugimoto K.
    Seimitsu Kogaku Kaishi/Journal of the Japan Society for Precision Engineering, 2011, 77 (03): : 284 - 289
  • [40] Effect of Native Oxide on Polycrystalline Silicon CMP
    Shin, Woonki
    Cho, Hanchul
    Lee, Hojun
    Jeong, Haedo
    JOURNAL OF THE KOREAN PHYSICAL SOCIETY, 2009, 54 (03) : 1077 - 1081