A novel multiple-valued CMOS flip-flop employing multiple-valued clock

被引：4
|
作者：
Xia, YS
Wang, LY
Almaini, AEA
机构：
[1] Napier Univ, Sch Engn, Edinburgh EH10 5DT, Midlothian, Scotland
[2] Ningbo Univ, Sch Informat & Engn Sci, Ningbo 315211, Peoples R China
来源：
JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY | 2005年 / 20卷 / 02期
关键词：
CMOS; flip-flops; multiple-valued clock; multiple-valued logic;
D O I：
10.1007/s11390-005-0237-4
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterized by improved storage capacity, flexible logic structure and reduced power dissipation.
引用
收藏
页码：237 / 242
页数：6
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