A compact model for analysis and design of on-chip power network with decoupling capacitors

A compact model for analysis and design of the power distribution network with on-chip decoupling capacitor for high-power blocks is presented. The model is applied to a high-density content addressable memory (CAM) for verification. Utilizing HSIM, a complete power system including CAM block is simulated The simulation results confirm the accuracy of the compact model, which includes transient and steady slate voltage drops in the power distribution network Utilizing the compact model, a new design space for the power distribution network is proposed For given system-level parameters, such as power supply voltage, pin inductance, and system clock frequency, the new design space helps the designer to optimize the power distribution network for high-power blocks such as CAM. In particular, it enables the designer to quantify the minimum on-chip decoupling capacitor needed Finally, the impact of system level parameters on the design space is presented It is shown that the design space shrinks with the advancing technology This imposes the light restriction for high-end technology chip designer to meet the requirements for both transient and steady state noises.