Design Challenges and Methodologies in 3D Integration for Neuromorphic Computing Systems

Neuromorphic computing is an emerging technology that describes the biological neural systems and implementation of its electrical model in complementary metal oxide semiconductor (CMOS) VLSI systems. As the neural networks are wire dominated complicated system with myriad interconnected elements, it requires massively parallel processing for the computational task. However, the hardware implementation experiences some critical challenges and unsurmountable obstacles by using 2D planar circuits. Therefore, the potential three dimensional integration technology can be applied in hardware implementation of neuromorphic computing that provides a sustainable and promising alternative to the existing conventional integrated circuit (IC) technology by allowing vertical stacking of dies. 3D hardware interconnection between the neural layers not only offer high device interconnection density with greater reduction in parasitic, it also provides improved channel bandwidth using fast and energy efficient links with excellent distribution and communication among the neuron layers. Beyond these opportunities, it needs a thorough investigation to explore all the design issues and critical challenges for successful implementation of 3D neuromorphic computation for high performance application. In this work, we studied the design challenges of the 3D integration technology for neuromorphic computing systems, and possible ways to overcome the limitation of well-connected synaptic system.