Challenges in 3D Integration

被引：3

作者：

Koyanagi, Mitsumasa ^{[1
]}

Lee, Kang Wook ^{[1
]}

Fukushima, Takafumi ^{[1
]}

Tanaka, Tetsu ^{[2
]}

机构：

[1] Tohoku Univ, New Ind Creat Hatchery Ctr, Sendai, Miyagi 9808579, Japan

[2] Tohoku Univ, Grad Sch Biomed Engn, Sendai, Miyagi 9808579, Japan

来源：

SILICON COMPATIBLE MATERIALS, PROCESSES, AND TECHNOLOGIES FOR ADVANCED INTEGRATED CIRCUITS AND EMERGING APPLICATIONS 3 | 2013年 / 53卷 / 03期

基金：

日本学术振兴会;

关键词：

TECHNOLOGY;

D O I：

10.1149/05303.0237ecst

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

Three-dimensional (3D) LSIs using TSVs are indispensable to achieve high performance and low power LSIs with smaller form factor. A wafer-to-wafer (WtW) technology is suitable for stacking chips with high production yield such as DRAM since the overall yield after stacking rapidly decreases as the number of stacking layers increases. The chip-to-wafer (CtW) is suitable for stacking known good dies (KGDs). In addition, chips with different size which are fabricated using different process technologies can be stacked in the CtW technology. The inherent problem in the CtW technology, however, is low production throughput. To solve these problems, we have proposed a new 3D heterogeneous integration technology called a super-chip technology using self-assembly and electrostatic (SAE) bonding method.

引用

页码：237 / 244

页数：8

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