Without a reference clock wide tuning range clock and data recovery circuit

This paper describes the design and fabrication of a clock and data recovery circuit (CDR). This clock and data recovery circuit utilizes a linear phase detector (PD) and full-rate frequency detector (FD), a self-biased ring voltage controlled oscillator (VCO). The proposed CDR can also remove virtually all of the process technology and environmental variability by using a self-biasing method. The proposed CDR circuit can achieve a wide acquisition range without using the reference clock. A ring VCO used in this CDR circuit has a wide operating frequency range of 250 MHz to 2.0 GHz. The CDR circuit has been fabricated in a standard 0.18 mu m CMOS technology. It occupies an active area of 1 x 1mm(2) and consumes 120 mW from a single 1.8V supply.