3D TSV Mid-End Processes and Assembly/Packaging Technology

Increasing demand for new and more advanced electronic products with a smaller form factor, superior functionality and performance with a lower overall cost has driven semiconductor industry to develop more innovative and emerging advanced packaging technologies. One of the hottest topics in the semiconductor industry today is a 3D packaging using Through Silicon Via (TSV) technology. Driven by the need for improved electrical performance or the reduction of timing delays, methods to use short vertical interconnects have been developed to replace the long interconnects found in 2D packaging. The industry is gearing up to move from technology path finding phase for TSV into commercialization phase, where economic realities will determine the technologies that can be adopted. Choosing the right process equipment and materials, combined with innovative design solutions addressing thermal and electrical issues will be the key success factors. This paper addresses TSV middle-end process as well as TSV assembly/packaging process. Latest developments in the key elements of 3D Si integration such as backside via reveal and thin wafer handling. The status of "bridge" technologies such as interposers and TSV substrates as an interim play prior to full productization of the active Si TSV approach is reviewed with specific examples of configurations approaching volume production in real products. For TSV assembly/packaging, microbump bonding and reliability characterization will be discussed. TSV Packaging challenges and experimental results will be presented for CTC (Chip-to-Chip), CTW (Chip-to-Wafer) bonding with ultra fine pitch microbump interconnections in this paper. Integrating TSV and IPD technology in an eWLB design delivers clear advantages such as advanced heterogeneous system integration, higher electrical performance and reduced form factor packaging. The ability to integrate TSV and IPD with eWLB technology opens up a wide range of possible design configurations for SiP and 3D packaging at the silicon level.