Instruction fetch mechanism for PN-superscalar

PN processor is the one of small parallelism computing processor which executes a parallel program scheduled statically. A program for PN processor consists of a few threads whose instructions are arranged with its function. And the possibility of parallel execution is presented explicitly by specifying all of data dependencies. In the early design, the instruction fetch mechanism of the PN processor was idealized. So we have introduced a new instruction fetch mechanism into PN processor. This paper describes the basic design of this new instruction fetch mechanism as well as an execution trace example.