Instruction fetch mechanism for PN-superscalar

被引：0

作者：

Okamoto, S ^{[1
]}

Sowa, M ^{[1
]}

机构：

[1] Univ Electrocommun, Grad Sch Informat Syst, Chofu, Tokyo 182, Japan

来源：

INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-III, PROCEEDINGS | 1997年

关键词：

instruction-level parallel computation; PN-Superscalar; instruction fetch;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

PN processor is the one of small parallelism computing processor which executes a parallel program scheduled statically. A program for PN processor consists of a few threads whose instructions are arranged with its function. And the possibility of parallel execution is presented explicitly by specifying all of data dependencies. In the early design, the instruction fetch mechanism of the PN processor was idealized. So we have introduced a new instruction fetch mechanism into PN processor. This paper describes the basic design of this new instruction fetch mechanism as well as an execution trace example.

引用

页码：1406 / 1410

页数：5

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