Performance impact of task-to-task communication protocol in Network-on-Chip

被引:0
|
作者
Bagherzadeh, Nader [1 ]
Matsuura, Masaru [2 ]
机构
[1] Univ Calif Irvine, Irvine, CA 92717 USA
[2] Sony Corp, Tokyo, Japan
关键词
D O I
10.1109/ITNG.2008.109
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Network-on-Chip (NoC) is a strong candidate for scalable interconnect design of Multi-Processor System-on-Chip (MPSoC). Software tasks of MPSoC require a certain protocol to communicate with each other In NoC such a communication protocol should be handled at Network Interface and/or Processor Element level and it is expected that different protocols show their trade-offs. In consideration of the above, we employed two types of basic protocol and investigated their performance impact. The contribution of this work is to quantitatively evaluate effectiveness of using separate communication protocols depending on the task structure.
引用
收藏
页码:1101 / +
页数:3
相关论文
共 50 条
  • [21] A Cycle-Accurate Network-on-Chip Simulator with Support for Abstract Task Graph Modeling
    Joseph, Jan Moritz
    Pionteck, Thilo
    2014 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP (SOC), 2014,
  • [22] Energy-Aware Task Allocation for Network-on-Chip Based Heterogeneous Multiprocessor Systems
    Huang, Jia
    Buckl, Christian
    Raabe, Andreas
    Knoll, Alois
    PROCEEDINGS OF THE 19TH INTERNATIONAL EUROMICRO CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING, 2011, : 447 - 454
  • [23] Low-Overhead Network-on-Chip Support for Location-Oblivious Task Placement
    Kim, Gwangsun
    Lee, Michael Mihn-Jong
    Kim, John
    Lee, Jae W.
    Abts, Dennis
    Marty, Michael
    IEEE TRANSACTIONS ON COMPUTERS, 2014, 63 (06) : 1486 - 1499
  • [24] Distributed Thermal-Aware Task Scheduling for 3D Network-on-Chip
    Cui, Yingnan
    Zhang, Wei
    Yu, Hao
    2012 IEEE 30TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2012, : 494 - 495
  • [25] Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip
    Liu, Weichen
    Yang, Lei
    Jiang, Weiwen
    Feng, Liang
    Guan, Nan
    Zhang, Wei
    Dutt, Nikil
    IEEE TRANSACTIONS ON COMPUTERS, 2018, 67 (12) : 1818 - 1834
  • [26] Communication Power Optimization for Network-on-Chip Architectures
    Shin, Dongkun
    Kim, Jihong
    JOURNAL OF LOW POWER ELECTRONICS, 2006, 2 (02) : 165 - 176
  • [27] Stochastic Automata Network Based Approach for Performance Evaluation of Network-on-Chip Communication Architecture
    Deshmukh, Ulhas
    Sahula, Vineet
    IEEE ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2010), 2010, : 351 - 356
  • [28] Dynamic Task Mapping and Scheduling with Temperature-Awareness on Network-on-Chip based Multicore Systems
    Paul, Suraj
    Chatterjee, Navonil
    Ghosal, Prasun
    JOURNAL OF SYSTEMS ARCHITECTURE, 2019, 98 : 271 - 288
  • [29] Cost Aware Task Scheduling And Core Mapping on Network-on-Chip topology using Firefly Algorithm
    Umamaheswari, S.
    Kirthiga, Indu K.
    Abinaya, B. S.
    Ashwin, D.
    2013 INTERNATIONAL CONFERENCE ON RECENT TRENDS IN INFORMATION TECHNOLOGY (ICRTIT), 2013, : 657 - 662
  • [30] Dynamic task allocation and scheduling with contention-awareness for Network-on-Chip based multicore systems
    Paul, Suraj
    Chatterjee, Navonil
    Ghosal, Prasun
    JOURNAL OF SYSTEMS ARCHITECTURE, 2021, 115