Interconnect Challenges for 3D Multi-cores: from 3D Network-on-Chip to Cache Interconnects

With the era of massive multi-core architecture targeting cloud computing for high end performances or advanced consumer electronics with tighter power consumption constraints, 3D integration technology will allow to design large scale multi-core. Thanks to advanced available 3D technology, it will be possible to maintain overall power consumption budget, increase chip to chip bandwidth, and preserve overall system cost by smart system partitioning. One of the main challenge of such multi-cores is clearly the interconnect infrastructure. For designing such 3D multi-cores, it is required to address two primary concerns: the 3D physical link by itself, and advanced interconnects scaled to 3D. The paper present an overview of 3D interconnects with 3D asynchronous Network-on-Chip architectures, with focus on 3D asynchronous links, and advanced interconnect structures for memory caches in 3D.