A Block-Based Parallel Decoding Architecture for Convolutional Codes

被引：0

作者：

Su, Chengyi ^{[1
]}

Zhang, Yu ^{[1
]}

Pan, Changyong ^{[1
]}

Wan, Xiaofeng ^{[1
]}

机构：

[1] Tsinghua Univ, Dept Elect Engn, Tsinghua Natl Lab Informat Sci & Technol, State Key Lab Microwave & Digital Commun, Beijing 100084, Peoples R China

来源：

2010 5TH INTERNATIONAL ICST CONFERENCE ON COMMUNICATIONS AND NETWORKING IN CHINA (CHINACOM) | 2010年

关键词：

Convolutional Codes; Parallel Decoding; Viterbi algorithm; FPGA;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper delivers a block-based parallel convolutional decoding architecture in which several Viterbi decoders work concurrently to decode consecutive code blocks. Each code block contains a preamble and a postamble which are duplicate data from neighbor blocks. Preamble and postamble are beneficial to the continuity and correctness of decoding output. Simulation results demonstrate that this architecture has a negligible coding-gain loss, compared with the conventional Viterbi decoder. An FPGA implementation of this architecture achieves a throughput up to 1.2Gbps.

引用

页数：4

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