Device characteristics of sub-20 nm silicon nanotransistors

This paper presents a systematic simulation-based study on the design, performance, and scaling issues of sub-20 nm silicon nanotransistors. 3d-process simulation was used to generate silicon FinFET device structures with fin thickness L (T-fin) of 10 to 30 nm, fin height (H-fin) of 50 nm, channel length (Lg) of 10 to 50-nm, and gate oxide thickness (T-OX(eff)) of 1.5 nm. 3d-device simulation results show that for n-channel FinFETs with H-fin = 50 nm, threshold voltage (V-th) decreases as La decreases and V,h roll-of with decreasing L-g, is higher for thicker Tfin devices. The simulated drive current (I-DSAT) decreases as T-fin decreases for Lg less than or equal to 25 nm while I-DSAT increases as T-fin decreases for Lg greater than or equal to 25 nm. It is, also, found that for the devices with H-fin = 50 nm. the simulated subthreshold swing (S) increases as La decreases for all devices with 10 nm less than or equal to T-fin less than or equal to 30 nm and approaches to 60 mV/decade for Lg greater than or equal to 40 nm. Also, S decreases as T-fin decreases for Le, < 40 nm devices. The simulated data for 20 nm nFinFETs with H-fin = 50 nm, T-fin = 10 nm, and T-OX(eff) = 1.5 nm show an excellent device performance with V-th congruent to 0.13 V, I-DSAT congruent to 775 mu A/mu m, I-off congruent to 3 mu A/mu m, and S congruent to 83 mV/decade. Finally, the simulation results for 20 nm nFinFETs and the conventional nMOSFETs were compared. This study, clearly, demonstrates a superior performance and scalability of FinFETs down to near 10 nm regime.