A genetic algorithm based input state assignment technique for leakage power minimization during combinational logic synthesis

Leakage power consumption is of prime concern today especially for battery-driven portable digital systems at present technology level. Leakage power in logic gates is strongly dependent on input patterns. By a suitable choice of input patterns (known as input vector) in standby mode, leakage power consumption can be greatly reduced. In this paper we have presented a genetic algorithm based input vector selection for combinational logic synthesis. We have also carried out a method to adopt high V-T transistors wherever there is a gate with worst-case leakage even after applying proper input vector, while maintaining the delay constraint or with small performance degradation. On an average we found that the proposed IVC technique gives 17.15% improvement in leakage power reduction over random average power and with high VT transistors the improvement is as high as 32.49%.