High-Speed Pseudo-CMOS Circuits Using Bulk Accumulation a-IGZO TFTs

被引：57

作者：

Chen, Yuanfeng ^{[1
]}

Geng, Di ^{[1
]}

Mativenga, Mallory ^{[1
]}

Nam, Hyoungsik ^{[1
]}

Jang, Jin ^{[1
]}

机构：

[1] Kyung Hee Univ, Dept Informat Display, Adv Display Res Ctr, Seoul 130701, South Korea

来源：

IEEE ELECTRON DEVICE LETTERS | 2015年 / 36卷 / 02期

关键词：

a-IGZO TFTs; bulk accumulation; pseudo-CMOS; ring oscillator; THIN-FILM TRANSISTORS; GATE OFFSET STRUCTURE; ILLUMINATION; INSTABILITY;

D O I：

10.1109/LED.2014.2379700

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose a way to achieve high-speed circuits with dual-gate (DG) bulk-accumulation back-channel-etched (BCE) amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) using the pseudo-CMOS structure. The DG BCE a-IGZO TFTs exhibit field-effect mobility (mu(FE)), threshold voltage (V-th), and subthreshold swing of 30 +/- 3 cm(2)/Vs, 2 +/- 0.5 V, and 120 +/- 30 mV/decade, respectively. For input voltage (V-DD) of 20 V, seven-stage pseudo-CMOS ring oscillators implemented with the BCE bulk-accumulation a-IGZO TFTs show oscillation frequency of 6.51 MHz, which corresponds to a propagation delay time of 11 ns/stage and is faster than the 17 ns/stage delay of the fastest single-gate-driven ratioed coplanar a-IGZO TFT circuits.

引用

页码：153 / 155

页数：3

共 50 条

[21] A portable digital DLL for high-speed CMOS interface circuits
Garlepp, BW
Donnelly, KS
Kim, J
Chau, PS
Zerbe, JL
Huang, C
Tran, CV
Portmann, CL
Stark, D
Chan, YF
Lee, TH
Horowitz, MA
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (05) : 632 - 644
[22] Design of CMOS CML circuits for high-speed broadband communications
Green, MM
Singh, U
PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II: COMMUNICATIONS-MULTIMEDIA SYSTEMS & APPLICATIONS, 2003, : 204 - 207
[23] Prospects of CMOS technology for high-speed optical communication circuits
Razavi, B
GAAS IC SYMPOSIUM, TECHNICAL DIGEST 2001, 2001, : 3 - 6
[24] RADIATION RESPONSE OF HIGH-SPEED CMOS INTEGRATED-CIRCUITS
YUE, H
DAVISON, D
JENNINGS, RF
LOTHONGKAM, P
RINERSON, D
WYLAND, D
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1987, 34 (06) : 1464 - 1466
[25] Prospects of CMOS technology for high-speed optical communication circuits
Razavi, B
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (09) : 1135 - 1145
[26] On optimal tapering of FET chains in high-speed CMOS circuits
Ding, L
Mazumder, P
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2001, 48 (12) : 1099 - 1109
[27] A low-power scan driver using depletion-mode a-IGZO TFTs for high-resolution displays
1600, Blackwell Publishing Ltd (45):
[28] High-speed high-precision min/max circuits in CMOS technology
Carvajal, RG
Ramírez-Angulo, J
Martínez-Heredia, J
ELECTRONICS LETTERS, 2000, 36 (08) : 697 - 699
[29] Enhancing the Contact between a-IGZO and Metal by Hydrogen Plasma Treatment for a High-Speed Varactor (>30 GHz)
Park, Hyuk
Yun, Juyoung
Park, Seongmin
Ahn, In-sung
Shin, Gibeom
Seong, Suwon
Song, Ho-Jin
Chung, Yoonyoung
ACS APPLIED ELECTRONIC MATERIALS, 2022, 4 (04) : 1769 - 1775
[30] Design and characterization of high-speed CMOS pseudo-LVDS transceivers
Kondratenko, S. V.
INTERNATIONAL CONFERENCE ON PARTICLE PHYSICS AND ASTROPHYSICS (ICPPA-2015), PTS 1-4, 2016, 675

← 1 2 3 4 5 →