Carrier Mobility Enhancement of Symmetric Double Gate Junctionless Transistor

In this paper two techniques has been proposed for enhancement of carrier mobility in a Double Gate Junction Less Transistor (DG JLT). The first technique uses a composite gate insulator consisting of two dielectrics placed with diagonal symmetry. The dielectrics used here are SiO2 and HfO2 having dielectric constants of 3.9 and 22 respectively. In the second technique, a gradual variation of doping concentration has been maintained along the length of the channel region. Extensive simulation for the structures has been carried out using TCAD. Simulation study reveals that in case of the proposed structures, the mobility in the subthreshold region is much less while in the on state of the device shows much higher mobility as compared to the conventional devices. The structure that uses gradual variation of doping concentration in the channel shows best results among the proposed structures. Transfer characteristics comparison shows that the structure has better subthreshold characteristic also.