共 50 条
- [1] Superior Interface Trap Variability Immunity of Horizontally Stacked Si Nanosheet FET in Sub-3-nm Technology Node 2021 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS), 2021, : 161 - 164
- [2] Optimization of Ge Mole Fraction in Sacrificial Layers for Sub-3-nm Node Silicon Nanosheet FETs 2023 7TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE, EDTM, 2023,
- [5] Investigation of Self-Heating Effect in Forksheet FETs for Sub-3-nm Node 2023 7TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE, EDTM, 2023,
- [7] Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes SN Applied Sciences, 2021, 3
- [8] Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes SN APPLIED SCIENCES, 2021, 3 (05):