A scalable stepped gate sensing scheme for sub-100nm multilevel flash memory

被引：0
|
作者：
Bauer, M [1 ]
Tedrow, K [1 ]
机构：
[1] Intel Corp, Folsom, CA 95630 USA
来源：
2005 INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY | 2005年
关键词：
D O I：
10.1109/ICICDT.2005.1502580
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
As Flash memory cell size scales with lithography, the storage capacitance area scales resulting in the need to sense fewer electrons that are stored on a floating gate. A stepped-gate sensing scheme for NOR Flash memories with Multilevel storage will be presented. Stepped-gate sensing motivation, scalability advantages and implementation are discussed.
引用
收藏
页码：23 / 26
页数：4
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