A scalable stepped gate sensing scheme for sub-100nm multilevel flash memory

被引：0
|
作者：
Bauer, M [1 ]
Tedrow, K [1 ]
机构：
[1] Intel Corp, Folsom, CA 95630 USA
来源：
2005 INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY | 2005年
关键词：
D O I：
10.1109/ICICDT.2005.1502580
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
As Flash memory cell size scales with lithography, the storage capacitance area scales resulting in the need to sense fewer electrons that are stored on a floating gate. A stepped-gate sensing scheme for NOR Flash memories with Multilevel storage will be presented. Stepped-gate sensing motivation, scalability advantages and implementation are discussed.
引用
收藏
页码：23 / 26
页数：4
相关论文
共 50 条
  • [21] Application of Cr-less mask technology for sub-100nm gate with single exposure
    Kim, SH
    Chung, DH
    Park, JS
    Shin, IK
    Choi, SW
    Sohn, JM
    Lee, JH
    Shin, HS
    Chen, F
    Van Den Broeke, D
    22ND ANNUAL BACUS SYMPOSIUM ON PHOTOMASK TECHNOLOGY, PTS 1 AND 2, 2002, 4889 : 568 - 578
  • [22] Next generation scanner for sub-100nm lithography
    Fujita, I
    Sakai, F
    Uzawa, S
    OPTICAL MICROLITHOGRAPHY XVI, PTS 1-3, 2003, 5040 : 811 - 821
  • [23] Patterning sub-100nm features for submicron devices
    Kavak, H
    Goodberlet, JG
    NANOENGINEERED NANOFIBROUS MATERIALS, 2004, 169 : 529 - 534
  • [24] Approach for physical design in sub-100nm era
    Masuda, H
    Okawa, S
    Aoki, M
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 5934 - 5937
  • [25] Copper contact technology for sub-100nm contacts
    Demuynck, Steven
    Zhao, Chao
    Van den Bosch, Geert
    Hinomura, Toru
    Tokei, Zsolt
    Beyer, Gerald P.
    ADVANCED METALLIZATION CONFERENCE 2007 (AMC 2007), 2008, 23 : 171 - 177
  • [26] Electrical properties of sub-100nm SiGe nanowires
    BHamawandi
    MNoroozi
    GJayakumar
    AErgl
    KZahmatkesh
    MSToprak
    HHRadamson
    Journal of Semiconductors, 2016, 37 (10) : 14 - 19
  • [27] Sub-100nm interconnects using multistep plating
    Yang, MX
    Mao, DX
    Yu, CM
    Dukovic, J
    Xi, M
    SOLID STATE TECHNOLOGY, 2003, 46 (10) : 37 - +
  • [28] Improvement of pattern collapse in sub-100nm nodes
    Jung, MH
    Lee, SH
    Kim, HW
    Woo, SG
    Cho, HK
    Han, WS
    ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XX, PTS 1 AND 2, 2003, 5039 : 1298 - 1303
  • [29] Electrical properties of sub-100nm SiGe nanowires
    B.Hamawandi
    M.Noroozi
    G.Jayakumar
    A.Ergül
    K.Zahmatkesh
    M.S.Toprak
    H.H.Radamson
    Journal of Semiconductors, 2016, (10) : 14 - 19
  • [30] Sub-100nm features with conformable contact photolithography
    不详
    SOLID STATE TECHNOLOGY, 2000, 43 (04) : 26 - +
12345