Logic design for on-chip test clock generation - Implementation details and impact on delay test quality

被引：27

作者：

Beck, M ^{[1
]}

Barondeau, O ^{[1
]}

Kaibel, M ^{[1
]}

Poehl, F ^{[1
]}

Lin, XJ ^{[1
]}

Press, R ^{[1
]}

机构：

[1] Infineon Technol AG, D-81541 Munich, Germany

来源：

DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/DATE.2005.199

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given.

引用

页码：56 / 61

页数：6

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