Enhanced TED: A new data structure for RTL verification

被引：1

作者：

Lotfi-Kamran, P. ^{[1
]}

Massoumi, M. ^{[1
]}

Mirzaei, M. ^{[2
]}

Navabi, Z. ^{[1
]}

机构：

[1] Univ Tehran, Sch Elect & Comp Engn, Tehran 14174, Iran

[2] Sharif Univ Technol, Sch Elect Engn, Tehran, Iran

来源：

21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/VLSI.2008.108

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This work provides a canonical representation for manipulation of RTL designs. Work has already been done on a canonical and graph-based representation called Taylor Expansion Diagram (TED). Although TED can effectively be used to represent arithmetic expressions at the word-level, it is not memory efficient in representing bit-level logic expressions. In addition, TED cannot represent Boolean expressions at the word-level (vector-level). In this paper, we present modifications to TED that will improve its ability for bit-level logic representation while enhancing its robustness to represent word-level Boolean expressions. It will be shown that for bit-level logic expressions, the Enhanced TED (ETED) performs the same as the BDD representation.

引用

页码：481 / +

页数：2

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