Enhanced TED: A new data structure for RTL verification

被引：1

作者：

Lotfi-Kamran, P. ^{[1
]}

Massoumi, M. ^{[1
]}

Mirzaei, M. ^{[2
]}

Navabi, Z. ^{[1
]}

机构：

[1] Univ Tehran, Sch Elect & Comp Engn, Tehran 14174, Iran

[2] Sharif Univ Technol, Sch Elect Engn, Tehran, Iran

来源：

21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/VLSI.2008.108

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This work provides a canonical representation for manipulation of RTL designs. Work has already been done on a canonical and graph-based representation called Taylor Expansion Diagram (TED). Although TED can effectively be used to represent arithmetic expressions at the word-level, it is not memory efficient in representing bit-level logic expressions. In addition, TED cannot represent Boolean expressions at the word-level (vector-level). In this paper, we present modifications to TED that will improve its ability for bit-level logic representation while enhancing its robustness to represent word-level Boolean expressions. It will be shown that for bit-level logic expressions, the Enhanced TED (ETED) performs the same as the BDD representation.

引用

页码：481 / +

页数：2

共 50 条

[1] TED+: A data structure for microprocessor verification
Lotfi-Kamran, Pejman
Hosseinabady, Mohammad
Shojaei, Hamid
Massoumi, Mehran
Navabi, Zainalabedin
ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, : 567 - 572
[2] A New Way to Generate Video Test Data for PCTV Receiver Chip RTL Verification
Wang Guangde
Miao Fang
PROCEEDINGS OF THE SECOND INTERNATIONAL SYMPOSIUM ON TEST AUTOMATION & INSTRUMENTATION, VOLS 1-2, 2008, : 656 - 660
[3] VERIFICATION OF THE TED CATHODE MODELS BY LONGTERM LIFETEST DATA
Brueck, Manfred
Hilble, Thomas
Morel, Stephane
Roquais, Jean-Michel
Seidel, Harald
2009 IEEE INTERNATIONAL VACUUM ELECTRONICS CONFERENCE, 2009, : 527 - 527
[4] Taylor Expansion Diagrams: A new representation for RTL verification
Ciesielski, M
Kalla, P
Zeng, ZH
Rouzeyre, B
SIXTH IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS, 2001, : 70 - 75
[5] K*BMDs: A new data structure for verification
Drechsler, R
Becker, B
Ruppertz, S
EUROPEAN DESIGN & TEST CONFERENCE 1996 - ED&TC 96, PROCEEDINGS, 1996, : 2 - 8
[6] A new RTL debugging methodology in FPGA-based verification platform
Yang, SJ
Shim, H
Yang, WS
Kyung, CM
PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004, : 180 - 183
[7] TED thermo electrical designer: a new physical design verification tool
Sokolowska, E
Barszcz, M
Kaminska, B
6th International Symposium on Quality Electronic Design, Proceedings, 2005, : 164 - 168
[8] Formal Probabilistic Timing Verification in RTL
Kumar, Jayanand Asok
Vasudevan, Shobha
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2013, 32 (05) : 788 - 801
[9] Constraints decomposition for RTL verification by SMT
Zhao, Yanni
Bian, Jinian
Deng, Shujun
Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics, 2010, 22 (02): : 234 - 239
[10] Reducing Verification Overhead with RTL slicing
Ou, Jen-Chieh
Saab, Daniel G.
Qiang, Qiang
Abraham, Jacob A.
GLSVLSI'07: PROCEEDINGS OF THE 2007 ACM GREAT LAKES SYMPOSIUM ON VLSI, 2007, : 399 - 404

← 1 2 3 4 5 →