Two modeling techniques for CMOS circuits to enhance test generation and fault simulation for bridging faults

被引：1
|
作者：
Lee, KJ [1 ]
Tang, JJ [1 ]
机构：
[1] NATL CHENG KUNG UNIV,DEPT ELECT ENGN,TAINAN,TAIWAN
来源：
PROCEEDINGS OF THE FIFTH ASIAN TEST SYMPOSIUM (ATS '96) | 1996年
关键词：
D O I：
10.1109/ATS.1996.555154
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：165 / 170
页数：6
相关论文
共 50 条
  • [1] Test generation for current testing of bridging faults in CMOS VLSI circuits
    Lee, T
    Hajj, IN
    38TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2, 1996, : 326 - 329
  • [2] Precise test generation for resistive bridging faults of CMOS combinational circuits
    Maeda, T
    Kinoshita, K
    INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS, 2000, : 510 - 519
  • [3] FAULT SIMULATION OF UNCONVENTIONAL FAULTS IN CMOS CIRCUITS
    FAVALLI, M
    OLIVO, P
    DAMIANI, M
    RICCO, B
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1991, 10 (05) : 677 - 682
  • [4] A PRACTICAL APPROACH TO FAULT SIMULATION AND TEST-GENERATION FOR BRIDGING FAULTS
    ABRAMOVICI, M
    MENON, PR
    IEEE TRANSACTIONS ON COMPUTERS, 1985, 34 (07) : 658 - 663
  • [5] TEST-GENERATION FOR I-DDQ TESTING OF BRIDGING FAULTS IN CMOS CIRCUITS
    BOLLINGER, SW
    MIDKIFF, SF
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1994, 13 (11) : 1413 - 1418
  • [6] FAULT SIMULATION OF PARAMETRIC BRIDGING FAULTS IN CMOS ICS
    DALPASSO, M
    FAVALLI, M
    OLIVO, P
    RICCO, B
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1993, 12 (09) : 1403 - 1410
  • [7] An efficient I-DDQ test generation scheme for bridging faults in CMOS digital circuits
    Chen, TH
    Hajj, IN
    Rudnick, EM
    Patel, JH
    1996 IEEE INTERNATIONAL WORKSHOP ON IDDQ TESTING, DIGEST OF PAPERS, 1996, : 74 - 78
  • [8] Test Generation for Open and Delay Faults in CMOS Circuits
    Wu, Cheng-Hung
    Lee, Kuen-Jong
    Reddy, Sudhakar M.
    2017 INTERNATIONAL TEST CONFERENCE IN ASIA (ITC-ASIA), 2017, : 21 - 26
  • [9] Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits
    Lee, T
    Hajj, IN
    Rudnick, EM
    Patel, JH
    14TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1996, : 456 - 462
  • [10] Simulation and generation of IDDQ tests for bridging faults in combinational circuits
    Chakravarty, S
    Thadikaran, PJ
    IEEE TRANSACTIONS ON COMPUTERS, 1996, 45 (10) : 1131 - 1140
12345