High-level optimization of pipeline design

被引：2

作者：

Campbell, JPL ^{[1
]}

Day, NA ^{[1
]}

机构：

[1] Univ Toronto, Dept Comp Sci, Toronto, ON, Canada

来源：

EIGHTH IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/HLDVT.2003.1252473

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We describe an automatic method for synthesizing pipelined processors that optimizes throughput and automatically resolves control and data hazards. We present rules that describe how to resolve hazards based on the data dependencies between functional units. We demonstrate our method by showing optimal pipeline configurations of the DLX.

引用

页码：43 / 48

页数：6

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