Error probability in synchronous digital circuits due to power supply noise

被引：2

作者：

Martorell, Ferran ^{[1
]}

Pons, Marc ^{[1
]}

Rubio, Antonio ^{[1
]}

Moll, Francesc ^{[1
]}

机构：

[1] Univ Politecn Cataluna, Dept Elect Engn, Barcelona, Spain

来源：

2007 INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA | 2007年

关键词：

error probability; CMOS synchronous circuits; power supply noise;

D O I：

10.1109/DTIS.2007.4449513

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered gives the timing violation error probability as a new design quality factor in front of conventional techniques that assume the full perfection of the circuit. The evaluation of the error bound can be useful for new design paradigms where retry and self-recovering techniques are being applied to the design of high performance processors. The method here described allows to evaluate the performance of these techniques by means of calculating the expected error probability in terms of power supply distribution quality.

引用

页码：170 / 175

页数：6

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