Error probability in synchronous digital circuits due to power supply noise

被引：2

作者：

Martorell, Ferran ^{[1
]}

Pons, Marc ^{[1
]}

Rubio, Antonio ^{[1
]}

Moll, Francesc ^{[1
]}

机构：

[1] Univ Politecn Cataluna, Dept Elect Engn, Barcelona, Spain

来源：

2007 INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA | 2007年

关键词：

error probability; CMOS synchronous circuits; power supply noise;

D O I：

10.1109/DTIS.2007.4449513

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered gives the timing violation error probability as a new design quality factor in front of conventional techniques that assume the full perfection of the circuit. The evaluation of the error bound can be useful for new design paradigms where retry and self-recovering techniques are being applied to the design of high performance processors. The method here described allows to evaluate the performance of these techniques by means of calculating the expected error probability in terms of power supply distribution quality.

引用

页码：170 / 175

页数：6

共 50 条

[1] Power supply noise and logic error probability
Andrade, Dennis
Martorell, Ferran
Pons, Marc
Moll, Francesc
Rubio, Antonio
[J]. 2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3, 2007, : 152 - 155
[2] Behavioral Modeling of Timing Slack Variation in Digital Circuits Due to Power Supply Noise
Na, Taesik
Mukhopadhyay, Saibal
[J]. PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016, : 281 - 284
[3] PROBABILITY OF ERROR DUE TO INTERSYMBOL INTERFERENCE AND GAUSSIAN NOISE IN DIGITAL COMMUNICATION SYSTEMS
SHIMBO, O
CELEBILER, MI
[J]. IEEE TRANSACTIONS ON COMMUNICATION TECHNOLOGY, 1971, CO19 (02): : 113 - +
[4] On the Comparison of Synchronous versus Asynchronous Circuits under the Scope of Conducted Power-Supply Noise
Cristofoli, L. F.
Henglez, A.
Benfica, J.
Bolzani, L.
Vargas, F.
Atienza, A.
Silva, F.
[J]. 2010 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY & TECHNICAL EXHIBITION ON EMC RF/MICROWAVE MEASUREMENTS & INSTRUMENTATION, 2010, : 1047 - 1050
[5] Reduction of switching noise and power supply currents in digital circuits with directed data flow
Raic, D
[J]. INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS, 2002, 32 (04): : 306 - 310
[6] ANALYSIS OF POWER SUPPLY NOISE MITIGATION CIRCUITS
Charania, Tasreen
Chuang, Pierce
Opal, Ajoy
Sachdev, Manoj
[J]. 2011 24TH CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (CCECE), 2011, : 1250 - 1255
[7] Power supply noise analysis in DSM circuits
He Jianchun
Jia Lixin
Liu Sheng
[J]. IEEE 2007 INTERNATIONAL SYMPOSIUM ON MICROWAVE, ANTENNA, PROPAGATION AND EMC TECHNOLOGIES FOR WIRELESS COMMUNICATIONS, VOLS I AND II, 2007, : 1416 - 1419
[8] Measurements of digital signal delay variation due to dynamic power supply noise
Fukazawa, Mitsuya
Nagata, Makoto
[J]. 2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS, 2005, : 165 - 168
[9] Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits
Limbrick, Daniel B.
Yue, Suge
Robinson, William H.
Bhuva, Bharat L.
[J]. 2011 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT), 2011, : 103 - 111
[10] An accurate and efficient estimation of switching noise in synchronous digital circuits
Habal, HM
Fiez, TS
Mayaram, K
[J]. 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 485 - 488

← 1 2 3 4 5 →