共 50 条
- [2] Reduction of simultaneous switching noise in digital circuits [J]. 24TH NORCHIP CONFERENCE, PROCEEDINGS, 2006, : 187 - +
- [3] Effects of digital switching noise on analog circuits performance [J]. 2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3, 2007, : 160 - 163
- [4] Estimation of maximum switching activity in digital VLSI circuits [J]. 40TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 1998, : 1130 - 1133
- [6] Error probability in synchronous digital circuits due to power supply noise [J]. 2007 INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA, 2007, : 170 - 175
- [7] Impact of simultaneous switching noise on the static behavior of digital CMOS circuits [J]. PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM, 2007, : 239 - 244
- [8] Accurate modeling of simultaneous switching noise in low voltage digital VLSI [J]. ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 6: CIRCUITS ANALYSIS, DESIGN METHODS, AND APPLICATIONS, 1999, : 210 - 213
- [9] An application of self-timed circuits to the reduction of switching noise in analog-digital circuits [J]. INTEGRATED CIRCUIT DESIGN, PROCEEDINGS: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2000, 1918 : 295 - 305
- [10] Estimation of on-chip simultaneous switching noise in VDSM CMOS circuits [J]. 2000 INTERNATIONAL CONFERENCE ON MODELING AND SIMULATION OF MICROSYSTEMS, TECHNICAL PROCEEDINGS, 2000, : 313 - 316