Estimation of on-chip simultaneous switching noise in VDSM CMOS circuits

被引：0

作者：

Tang, KT ^{[1
]}

Friedman, EG ^{[1
]}

机构：

[1] Univ Rochester, Dept Elect & Comp Engn, Rochester, NY 14627 USA

来源：

2000 INTERNATIONAL CONFERENCE ON MODELING AND SIMULATION OF MICROSYSTEMS, TECHNICAL PROCEEDINGS | 2000年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

On-chip simultaneous switching noise (SSN) has become an important issue in the design of power distribution networks in current VLSI/ULSI circuits. An analytical expression characterizing the simultaneous switching noise voltage is presented here based on a lumped RLC model. The waveform describing the SSN voltage is quite close to the waveform obtained from SPICE. The peak value of the simultaneous switching noise voltage based on this analytical expression is within 10% as compared to SPICE simulations.

引用

页码：313 / 316

页数：4

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