A Low-Cost and Low-Power Time-to-Digital Converter Using Triple-Slope Time Stretching

被引：19

作者：

Kim, Manho ^{[1
]}

Lee, Hyunjoong ^{[2
]}

Woo, Jong-Kwan ^{[2
]}

Xing, Nan ^{[1
]}

Kim, Min-Oh ^{[2
]}

Kim, Suhwan ^{[2
]}

机构：

[1] Seoul Natl Univ, Dept Elect Engn, Seoul 151742, South Korea

[2] Seoul Natl Univ, Dept Elect Engn, Seoul 151744, South Korea

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2011年 / 58卷 / 03期

关键词：

Dual-slope conversion; interpolator; time stretcher; time-to-digital converter (TDC); CMOS; PRECISION;

D O I：

10.1109/TCSII.2011.2106353

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this brief, we present a time-to-digital converter (TDC) in which a single interpolator is used to improve the resolution by time stretching. The interpolator is based on a triple-slope conversion. Without slowing down the measured event, this approach extensively reduces the chip area and the corresponding power consumption, as compared with the prior arts with two parallel time interpolators. A prototype was designed and fabricated in a 0.35-mu m CMOS digital process, and its core area merely occupies 0.126 mm(2). Measurements show that our TDC achieves a resolution of 357 ps while consuming 1.22m W with a 2.5-V supply. The dynamic range of the TDC exceeds 1.46 mu s. The measurement rate can achieve above 400 kS/s.

引用

页码：169 / 173

页数：5

共 50 条

[41] A novel time-based low-power pipeline analog to digital converter
Zarifi, Mohammad Hossein
Frounchi, Javad
Farshchi, Shahin
Judy, Jack W.
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2010, 62 (03) : 281 - 289
[42] Cost-Effective Time-to-Digital Converter Using Time-Residue Feedback
Lai, Jung-Chin
Hsu, Terng-Yin
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2017, 64 (06) : 4690 - 4700
[43] Variation tolerant high resolution and low latency time-to-digital converter
Henzler, S.
Koeppe, S.
Lorenz, D.
Kamp, W.
Kuenemund, R.
Schmitt-Landsiedel, D.
ESSCIRC 2007: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2007, : 194 - +
[44] A precise cyclic CMOS time-to-digital converter with low thermal sensitivity
Chen, CC
Chen, P
Hwang, CS
Chang, W
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2005, 52 (04) : 834 - 838
[45] A low power CMOS time-to-digital converter based on duty cycle controllable pulse stretcher
Chen, Chun-Chi
Chen, Poki
Shen, You-Sheng
ESSCIRC 2006: PROCEEDINGS OF THE 32ND EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2006, : 316 - +
[46] A Low Power 10-bit Time-to-Digital Converter Utilizing Vernier Delay Lines
Chen, Wei
Papavassiliou, Christos
UKSIM-AMSS 15TH INTERNATIONAL CONFERENCE ON COMPUTER MODELLING AND SIMULATION (UKSIM 2013), 2013, : 774 - 779
[47] A precise cyclic CMOS time-to-digital converter with low thermal sensitivity
Chen, CC
Chang, W
Chen, P
2004 IEEE NUCLEAR SCIENCE SYMPOSIUM CONFERENCE RECORD, VOLS 1-7, 2004, : 1364 - 1367
[48] A new successive approximation architecture for low-power low-cost CMOS A/D converter
Lin, CS
Liu, BD
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (01) : 54 - 62
[49] Measuring Metastability Using a Time-to-Digital Converter
Polzer, Thomas
Huemer, Florian
Steininger, Andreas
2017 20TH IEEE INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUIT & SYSTEMS (DDECS), 2017, : 116 - 121
[50] Low-Power Low-Cost Direct Digital Frequency Synthesizer Using 90 nm CMOS Technology
Ellaithy, Dina M.
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2022, 31 (11)

← 1 2 3 4 5 →