Variation tolerant high resolution and low latency time-to-digital converter

A high resolution time-to-digital converter (TDC) with low latency and low deadtime is proposed. A coarse time quantization derived from a differential inverter delay line is locally interpolated with passive voltage dividers. The high resolution TDC is monotonic by construction which makes the concept very robust against process variations. The feasibility is demonstrated with an 8-bit TDC with a resolution of 0.25 inverter delays in a 90nm low power CMOS technology. The resolution limits imposed by clock uncertainty and local variations are derived theoretically.