Circuit design compliance checking in VLSI circuits

被引：0

作者：

Lam, KN ^{[1
]}

Rusu, S ^{[1
]}

机构：

[1] L LOG DESIGN GRP,SUNNYVALE,CA 94089

来源：

NINTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE AND EXHIBIT, PROCEEDINGS | 1996年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：167 / 170

页数：4

共 50 条

[1] DESIGN AND SYNTHESIS OF SELF-CHECKING VLSI CIRCUITS
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[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1993, 12 (06) : 878 - 887
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[3] DESIGN RULE CHECKING AND VLSI
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[J]. INTEGRATION-THE VLSI JOURNAL, 1987, 5 (3-4) : 289 - 302
[4] Circuit schematic generation and optimization in VLSI circuits
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[5] DESIGN AND SIMULATION OF VLSI CIRCUITS
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[J]. HEWLETT-PACKARD JOURNAL, 1981, 32 (06): : 12 - &
[6] FLOORPLAN DESIGN OF VLSI CIRCUITS
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[7] Integrated approach for circuit and fault extraction of VLSI circuits
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Teixeira, IC
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[8] DESIGN OF VLSI ASYNCHRONOUS CIRCUITS FOR TESTABILITY
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[J]. INTERNATIONAL JOURNAL OF ELECTRONICS, 1988, 64 (06) : 859 - 868
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ELSAYED, EA
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[10] FAST STRUCTURED DESIGN OF VLSI CIRCUITS
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