Partially Adaptive Look-Ahead Routing for Low Latency Network-on-Chip

被引:0
|
作者
Najib, Nadera [1 ]
Monemi, Alireza [1 ]
Marsono, Muhammad Nadzir [1 ]
机构
[1] Univ Teknol Malaysia, Fac Elect Engn, Johor Baharu 81310, Malaysia
关键词
Partially adaptive routing; Low latency NoC router;
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Adaptive routing algorithms offer the ability to avoid congestion by supporting multiple paths between a source and destination. However, supporting adaptive routing for low latency routers is a challenge due to the computation of routing algorithm in one router in advanced (i.e. look-ahead routing). This paper presents an RTL architecture of partially adaptive look-ahead routing algorithm on a recently proposed low latency, virtual channel wormhole Network-on-Chip (NoC) router. In our proposed design, each router pre-computes the preferred output ports based on its local congestion and transfers the preferred output ports to the neighbouring routers. These preferred output ports are used in the look-ahead routing to select the optimal output port for the packet. We compare our proposed partially adaptive routing architecture with the reference design using look-ahead XY routing algorithm under matrix-transpose traffic and obtained 10% improvement at maximum injection rate. Our proposed routing algorithm has negligible area overhead (<2%) while has no influence on maximum operating frequency.
引用
收藏
页数:5
相关论文
共 50 条
  • [21] A technique for low energy mapping and routing in network-on-chip architectures
    Srinivasan, K
    Chatha, KS
    ISLPED '05: PROCEEDINGS OF THE 2005 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2005, : 387 - 392
  • [22] An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip
    Salamat, Ronak
    Ebrahimi, Masoumeh
    Bagherzadeh, Nader
    23RD EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP 2015), 2015, : 392 - 395
  • [23] Transient Error Management for Partially Adaptive Router in Network-on-Chip (NoC)
    Yu, Qiaoyan
    Ampadu, Paul
    2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 1672 - 1675
  • [24] A Comparative Review of Adaptive Routing Approach for Network-on-Chip Router Architecture
    Zulkefli, F. W.
    Ehkan, P.
    Warip, M. N. M.
    Phing, Ng Yen
    Zakaria, F. F.
    RECENT TRENDS IN INFORMATION AND COMMUNICATION TECHNOLOGY, 2018, 5 : 247 - 254
  • [25] Bi-Objective Cost Function for Adaptive Routing in Network-on-Chip
    Gabis, Asma Benmessaoud
    Bomel, Pierre
    Sevaux, Marc
    IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS, 2018, 4 (02): : 177 - 187
  • [26] A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures
    Wang, Ling
    Song, Hui
    Jiang, Yingtao
    Zhang, Lihong
    COMPUTERS & ELECTRICAL ENGINEERING, 2009, 35 (06) : 846 - 855
  • [27] Virtual Channel and Switch Allocation for Low latency Network-on-Chip Routers
    Monemi, Alireza
    Ooi, Chia Yee
    Marsono, Muhammad Nadzir
    2015 IEEE 23RD ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM), 2015, : 234 - 234
  • [28] Look-Ahead VNF-FG Embedding Framework for Latency-Sensitive Network Services
    Recse, Akos
    Promwongsa, Nattakorn
    Ebrahimzadeh, Amin
    Afrasiabi, Seyedeh Negar
    Mouradian, Carla
    Li, Wubin
    Szabo, Robert
    Glitho, Roch H.
    IEEE TRANSACTIONS ON NETWORK AND SERVICE MANAGEMENT, 2023, 20 (03): : 2682 - 2697
  • [29] Traffic Allocation: An Efficient Adaptive Network-on-Chip Routing Algorithm Design
    Wang, Nan
    Valencia, Pedro
    2016 2ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER AND COMMUNICATIONS (ICCC), 2016, : 2015 - 2019
  • [30] Low Latency Network-on-Chip Router Using Static Straight Allocator
    Monemi, Alireza
    Ooi, Chia Yee
    Palesi, Maurizio
    Marsono, Muhammad Nadzir
    2016 3RD INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY, COMPUTER, AND ELECTRICAL ENGINEERING (ICITACEE), 2016, : 2 - 9