A 9.08 ENOB 10b 400MS/s Subranging SAR ADC with Subsetted CDAC and PDAS in 40nm CMOS

被引：6

作者：

Yu, Qiang ^{[1
]}

Zhou, Xiong ^{[1
]}

Hu, Kefeng ^{[1
]}

Huang, Zijian ^{[1
]}

Chen, Haiwen ^{[1
]}

Si, Xin ^{[1
]}

Yang, Jinda ^{[2
]}

Li, Qiang ^{[1
]}

机构：

[1] Univ Elect Sci & Technol China, Inst Integrated Circuits & Syst, Chengdu, Peoples R China

[2] Chengdu Sino Microelect Technol, Chengdu, Peoples R China

来源：

ESSCIRC 2021 - IEEE 47TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC) | 2021年

基金：

中国国家自然科学基金;

关键词：

SAR ADC; subranging; PDAS; dynamic circuit design;

D O I：

10.1109/ESSCIRC53450.2021.9567859

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work, a 10b 400MS/s single-channel SAR ADC is reported. Without an auxiliary sub-ADC, a subranging architecture is proposed, where only one comparator is used with the subsetted capacitive DAC (CDAC), eliminating the mismatch of comparators and saving area. For the subranging process, a partial detect-and-skip (PDAS) switching scheme is proposed, which improves both power efficiency and linearity without delay overhead. In addition, the dynamic logic circuits, including dynamic asynchronous loop (DAL) and dynamic SAR logic (DSL), are improved to reduce the power and logic propagation delay. Fabricated in a 40 nm CMOS process, this single-channel prototype operates at an enhanced sampling rate of 400 MS/s. At Nyquist, 56.4 dB SNDR and 73.1 dB SFDR are achieved. The ADC draws 3.46mW from a single 1.2V supply, leading to a FoMw of 16.0fJ/ conversion-step.

引用

页码：391 / 394

页数：4

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