共 50 条
- [31] Sub-10nm junction in InGaAs with sulfur mono-layer doping [J]. 2013 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), 2013,
- [34] Sub-10nm patterns defined by electron beam lithography and molecular liftoff [J]. ABSTRACTS OF PAPERS OF THE AMERICAN CHEMICAL SOCIETY, 2006, 231
- [36] A study of fabrication techniques for sub-10nm thin undulated polysilicon films [J]. 2003 INTERNATIONAL SEMICONDUCTOR CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2003, : 95 - 98
- [37] Towards High Performance Sub-10nm finW Bulk FinFET Technology [J]. 2016 46TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2016, : 131 - 134
- [38] Machine Learning-enhanced Multi-dimensional Co-Optimization of Sub-10nm Technology Node Options [J]. 2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2019,
- [40] Will Self-heating be Seriously Problematic in Sub-10nm Technology Nodes ? [J]. 2018 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2018,